With the development of high-speed logic circuits, data communication equipment has continued to move toward digital implementations. The progress of communication systems is in part due to performance increases and cost reductions of digital circuit technology. Digital systems, which are generally more reliable than analog systems in noisy communications environments, must still be protected from random noise events on communication channels. Data scramblers, check codes, error correction codes, and interleavers are common techniques for protecting data from noise. The two most commonly used types of forward error correction codes are block codes and convolutional codes. Block codes involve operations that depend on the current input message and are independent of previous encodings. In contrast, convolutional codes involve output sequences that depend not only on the current input message, but also on a number of past message blocks. Interleavers are also commonly used for controlling impulse noise, which is characterized by high-power, short-duration bursts. An interleaver is a device that rearranges the order of a sequence of input symbols, or a collection of bits. The classic use of interleaving is to randomize the location of errors introduced in signal transmission. Interleaving spreads a burst of errors out so that error correction circuits have a better chance of correcting the data. If a particular interleaver is used at the transmit end of a channel, the inverse of that interleaver must be used at the receive end to recover the original data. The inverse interleaver is referred to as a de-interleaver.
Turbo Convolutional Coding (TCC) is used in a large number of wireless communication systems, such as third generation (3G) wireless and code division multiple access (CDMA) environments. Turbo Convolutional Coding is an advanced Forward Error Correction (FEC) algorithm which provides a powerful mechanism for protecting data transmissions. The encoder generates a data stream consisting of two independently encoded data streams and a single un-encoded data stream. Two parity streams, which are weakly correlated due to the interleaving, are also provided to the decoder. In the decoder, the two parity streams are separately decoded with soft decision outputs, referred to as ‘extrinsic’ information. The strength of the turbo decoding results from the sharing of the extrinsic information in a number of iterations. The extrinsic information is passed from one parity-decoding step to the other for each iteration. However, the implementation of a TCC decoder is difficult, particularly when high data rates are involved. Conventional interleaver circuits have limitations and inefficiencies in determining how a next interleaver address is processed. As data rates increase, the challenges of implementing TCC decoders will also increase.
In data processing systems, blocks of data are often divided into windows of data which are processed in parallel. Multiple soft input, soft output (SISO) decoders, also called MAP decoders, may be operated in parallel to increase the throughput of the decoding process. For example, a data block of N bits may be divided into m windows. According to one conventional method of generating an interleaver address in a system processing parallel windows of data, the least significant bits of an interleaver address Pi(j) are used as the new interleaver address P′i(j) and the most significant bits are used as the window select signal Wi(j). One of the plurality of parallel decoders operates to decode a particular data window. However, conventional circuits implementing parallel decoders where the most significant bits of the interleaver address represent a window select value require the number of windows to be powers of two. That is, the data block is divided into m windows, where m is a power of two, and the first m−1 windows have lengths that are also powers of two while the last window has the remaining data. In addition to requiring additional circuitry for the multiple address generators, this method has an adverse impact on Bit Error Rate (BER) performance, especially when the length of the last window is small. In particular, a separate address generator is required for each MAP decoder, where the output for each address generator (i) is based upon modulo (mod) N for a data block having N bits, and (ii) will result in a next address having the same least significant bits for each address generator, but different most significant bits determining the window select value. Another conventional method to generate a new interleaver address and window select signal is through a look up table that is implemented in memory, such as a block random access memory (BRAM). However, the BRAM requirements may make it impractical to build the TCC circuit in certain integrated circuits, such as a programmable logic device.
Accordingly, there is a need for an improved circuit for and a method of generating an interleaver address in a circuit for decoding data.